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philips semiconductors pca9510; pca9511 hot swappable i 2 c and smbus bus buffer product data sheet supersedes data of 2003 dec 18 2004 oct 05 integrated circuits
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2 2004 oct 05 description the pca9510 and pca9511 are hot swappable i 2 c and smbus buffers that allows i/o card insertion into a live backplane without corrupting the data and clock buses. control circuitry prevents the backplane from being connected to the card until a stop command or bus idle occurs on the backplane without bus contention on the card. when the connection is made, the pca9510 and pca9511 provides bi-directional buffering, keeping the backplane and card capacitances isolated. the pca9511 rise time accelerator circuitry allows the use of weaker dc pull-up currents while still meeting rise time requirements, while the pca9510 has no rise time accelerator circuitry to prevent interference when there are multiple devices in the same system. the pca9510 and pca9511 incorporate a digital enable input pin, which enables the device when asserted high and forces the device into a low current mode when asserted low, and an open-drain ready output pin, which indicates that the backplane and card sides are connected together (high) or not (low). during insertion, the pca9510 (in only) and pca9511 sda and scl lines are precharged to 1 v to minimize the current required to charge the parasitic capacitance of the chip. the dynamic offset design of the pca9510/11/12/13/14 i/o drivers allow them to be connected to another pca9510/11/12/13/14 device in series or in parallel and to the a side of the pca9517. the pca9510/11/12/13/14 can not connect to the static offset i/os used on the pca9515/15a/16/16a/17 b side and pca9518. application ? cpci, vme, advancedtca cards and other multi-point backplane cards that are required to be inserted or removed from an operating system. features ? bi-directional buffer for sda and scl lines increases fanout and prevents sda and scl corruption during live board insertion and removal from multi-point backplane systems ? compatible with i 2 c standard mode, i 2 c fast mode, and smbus standards ? d v/ d t rise time accelerators on all sda and scl lines (pca9511 only) ? rise time accelerator threshold of 0.6 v ? active high enable input ? active high ready open-drain output ? high impedance sda and scl pins for v cc = 0 v ? 1 v precharge on all sda and scl lines (pca9510 in only) ? supports clock stretching and multiple master arbitration/synchronization ? operating power supply voltage range: 2.7 v to 5.5 v ? 5.5 v tolerant i/os ? 0 to 400 khz clock frequency ? esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115, and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jedec standard jesd78 which exceeds 100 ma ? package offer: so8, tssop8 (msop8) ordering information packages temperature range order code topside mark drawing number 8-pin plastic so 40 c to +85 c PCA9510D pca9510 sot96-1 8-pin plastic so 40 c to +85 c pca9511d pca9511 sot96-1 8-pin plastic tssop (msop) 40 c to +85 c PCA9510Dp 9510 sot505-1 8-pin plastic tssop (msop) 40 c to +85 c pca9511dp 9511 sot505-1 standard packing quantities and other packaging data is available at www.standardproducts.philips.com/packaging.
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 3 pin configuration 1 2 3 4 enable gnd sclin sdaout sdain ready 5 6 7 8 v cc sclout sw01045 top view figure 1. pin configuration. pin description pin symbol description 1 enable chip enable pin. grounding this pin puts the part in a low current (<1 m a) mode. it also disables the rise time accelerators, isolates sdain from sdaout and isolates sclin from sclout. 2 sclout serial clock output to and from the scl bus on the card. 3 sclin serial clock input to and from the scl bus on the backplane. 4 gnd ground. connect this pin to a ground plane for best results. 5 ready this is an open-drain output which pulls low when sdain and sclin are disconnected from sdaout and sclout, and turns off when the two sides are connected. 6 sdain serial data input to and from the sda bus on the backplane. 7 sdaout serial data output to and from the sda bus on the card. 8 v cc power supply. feature selection chart features pca9510 pca9511 pca9512 pca9513 pca9514 idle detect yes yes yes yes yes high impedance sda, scl pins for v cc = 0 v yes yes yes yes yes rise time accelerator circuitry on all sda and scl lines e yes yes yes yes rise time accelerator circuitry hardware disable pin for lightly loaded systems e e yes e e rise time accelerator threshold 0.8 v vs 0.6 v improves noise margin e e e yes yes ready open drain output yes yes e yes yes two v cc pins to support 5 v to 3.3 v level translation with improved noise margins e e yes e e 1 v precharge on all sda and scl lines in only yes yes e e 92 m a current source on sclin and sdain for picmg applications e e e yes e
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 4 typical application e pca9510 sclout sdaout r4 10 k w r3 10 k w r2 10 k w r1 10 k w c1 0.01 m f sclin sdain v cc (2.7 v to 5.5 v) 6 3 1 enable ready gnd 7 2 5 8 sw02149 4 r5 10 k w enable figure 2. typical application e pca9510 block diagram e pca9510 0.55v cc / 0.45v cc 2 sclout 0.5 pf rd s qb uvlo 20 pf stop bit and bus idle 130 m s delay 0.5 m a 1 enable uvlo 0.55v cc / 0.45v cc connect backplane-to-card connection connect 3 sclin connect 5 ready 4 gnd sw02150 100 k w rch2 100 k w rch1 connect 7 sdaout connect backplane-to-card connection 6 sdain 1 volt precharge 8 v cc enable connect connect figure 3. block diagram e pca9510
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 5 typical application e pca9511 sclout sdaout r4 10 k w r3 10 k w r2 10 k w r1 10 k w c1 0.01 m f sclin sdain v cc (2.7 v to 5.5 v) 6 3 1 enable ready gnd 7 2 5 8 sw02151 4 r5 10 k w enable figure 4. typical application e pca9511 block diagram e pca9511 0.55v cc / 0.45v cc 2 sclout 0.5 pf rd s qb uvlo 20 pf stop bit and bus idle 130 m s delay 0.5 m a 1 enable uvlo 0.55v cc / 0.45v cc connect 2 ma slew rate detector backplane-to-card connection 2 ma slew rate detector connect 3 sclin connect 5 ready 4 gnd sw01051 100 k w rch4 100 k w rch3 100 k w rch2 100 k w rch1 connect 7 sdaout connect 2 ma slew rate detector backplane-to-card connection 2 ma slew rate detector 6 sdain 1 volt precharge 8 v cc enable connect connect figure 5. block diagram e pca9511
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 6 operation start-up an under voltage/initialization circuit holds the parts in a disconnected state which presents high impedance to all sda and scl pins during power-up. a low on the enable pin also forces the parts into the low current disconnected state when the i cc is essentially zero. as the power supply is brought up and the enable is high or the part is powered and the enable is taken from low to high it enters an initialization state where the internal references are stabilized and the precharge circuit for pca9510 (in only) and pca9511 are enabled. at the end of the initialization state the astop bit and bus idleo detect circuit is enabled. with the enable pin high long enough to complete the initialization state and remaining high when all the sda and scl pins have been high for the bus idle time or when all pins are high and a stop condition is seen on the sdain and sclin pins, sdain is connected to sdaout and sclin is connected to sclout. the 1 v precharge circuitry is activated during the initialization and is deactivated when the connection is made. the precharge circuitry pulls up the sda and scl pins to 1 v through individual 100 k nominal resistors. this precharges the pins to 1 v to minimize the worst case disturbances that result from inserting a card into the backplane where the backplane and the card are at opposite logic levels. connect circuitry once the connection circuitry is activated, the behavior of sdain and sdaout as well as sclin and sclout become identical with each acting as a bidirectional buffer that isolates the input capacitance from the output bus capacitance while communicating the logic levels. a low forced on either sdain or sdaout will cause the other pin to be driven to a low by the part. the same is also true for the scl pins. noise between 0.7v cc and v cc is generally ignored because a falling edge is only recognized when it falls below 0.7v cc with a slew rate of at least 1.25 v/ m s. when a falling edge is seen on one pin the other pin in the pair turns on a pull down driver that is referenced to a small voltage above the falling pin. the driver will pull the pin down at a slew rate determined by the driver and the load initially, because it does not start until the first falling pin is below 0.7v cc . the first falling pin may have a fast or slow slew rate, if it is faster than the pull down slew rate then the initial pull down rate will continue. if the first falling pin has a slow slew rate then the second pin will be pulled down at its initial slew rate only until it is just above the first pin voltage the they will both continue down at the slew rate of the first. once both sides are low they will remain low until all the external drivers have stopped driving lows. if both sides are being driven low to the same value for instance, 10 mv by external drivers, which is the case for clock stretching and is typically the case for acknowledge, and one side external driver stops driving that pin will rise and rise above the nominal offset voltage until the internal driver catches up and pulls it back down to the offset voltage. this bounce is worst for low capacitances and low resistances, and may become excessive. when the last external driver stops driving a low, that pin will bounce up and settle out out just above the other pin as both rise together with a slew rate determined by the internal slew rate control and the rc time constant. as long as the slew rate is at least 1.25 v/ m s, when the pin voltage exceeds 0.6 v for the pca9511, the rise time accelerators circuits are turned on and the pull down driver is turned off. maximum number of devices in series each buffer adds about 0.065 v dynamic level offset at 25 c with the offset larger at higher temperatures. maximum offset (v os ) is 0.150 v. the low level at the signal origination end (master) is dependent upon the load and the only specification point is the i 2 c-bus specification of 3 ma will produce v ol < 0.4 v, although if lightly loaded the v ol may be ~ 0.1 v. assuming v ol = 0.1 v and v os = 0.1 v, the level after four buffers would be 0.5 v, which is only about 0.1 v below the threshold of the rising edge accelerator (about 0.6 v). with great care a system with four buffers may work, but as the v ol moves up from 0.1 v, noise or bounces on the line will result in firing the rising edge accelerator thus introducing false clock edges. generally it is recommended to limit the number of buffers in series to two. the pca9510 (rise time accelerator is permanently disabled) and the pca9512 (rise time accelerator can be turned off) are a little different with the rise time accelerator turned off because the rise time accelerator will not pull the node up, but the same logic that turns on the accelerator turns the pull-down off. if the v il is above ~ 0.6 v and a rising edge is detected, the pull-down will turn off and will not turn back on until a falling edge is detected; so if the noise is small enough it may be possible to use more than two pca9510 or pca9512 parts in series but is not recommended. master buffer a slave b buffer b slave c buffer c sw02353 common node figure 6. consider a system with three buffers connected to a common node and communication between the master and slave b that are connected at either end of buffer a and buffer b in series as shown in figure 6. consider if the v ol at the input of buffer a is 0.3 v and the v ol of slave b (when acknowledging) is 0.4 v with the direction changing from master to slave b and then from slave b to master. before the direction change you would observe v il at the input of buffer a of 0.3 v and its output, the common node, is ~ 0.4 v. the output of buffer b and buffer c would be ~ 0.5 v, but slave b is driving 0.4 v, so the voltage at slave b is 0.4 v. the output of buffer c is ~ 0.5 v. when the master pull-down turns off, the input of buffer a rises and so does its output, the common node, because it is the only part driving the node. the common node will rise to 0.5 v before buffer b's output turns on, if the pull-up is strong the node will bounce. if the bounce goes above the threshold for the rising edge accelerator ~ 0.6 v the accelerators on both buffer a and buffer c will fire contending with the output of buffer b. the node on the input of buffer a will go high as will the input node of buffer c. after the common node voltage is stable for a while the rising edge accelerators will turn off and the common node will return to ~ 0.5 v because the buffer b is still on. the voltage at both the master and slave c nodes would then fall to ~ 0.6 v until slave b turned off. this would not cause a failure on the data line as long as the return to 0.5 v on the common node ( ~ 0.6 v at the master and slave c) occurred before the data setup time. if this were the scl line, the parts on buffer a and buffer c would see a false clock rather than a stretched clock, which would cause a system error.
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 7 propagation delays the delay for a rising edge is determined by the combined pull-up current from the bus resistors and the rise time accelerator current source and the effective capacitance on the lines. if the pull-up currents are the same, any difference in rise time is directly proportional to the difference in capacitance between the two sides. the t plh may be negative if the output capacitance is less than the input capacitance and would be positive if the output capacitance is larger than the input capacitance, when the currents are the same. the t phl can never be negative because the output does not start to fall until the input is below 0.7v cc , and the output turn on has a non zero delay, and the output has a limited maximum slew rate, and even if the input slew rate is slow enough that the output catches up it will still lag the falling voltage of the input by the offset voltage. the maximum t phl occurs when the input is driven low with zero delay and the output is still limited by its turn on delay and the falling edge slew rate. the output falling edge slew rate is a function of the internal maximum slew rate which is a function of temperature. v cc and process, as well as the load current and the load capacitance. rise time accelerators during positive bus transitions a 2 ma current source is switched on to quickly slew the sda and scl lines high once the input level of 0.6 v for the pca9511 is exceeded. the rising edge rate should be at least 1.25 v/ m s to guarantee turn on of the accelerators. the pca9510 doesn't have any rise time accelerator circuitry. ready digital output this pin provides a digital flag which is low when either enable is low or the start-up sequence described earlier in this section has not been completed. ready goes high when enable is high and start-up is complete. the pin is driven by an open drain pull-down capable of sinking 3 ma while holding 0.4 v on the pin. connect a resistor of 10 k to v cc to provide the pull-up. enable low current disable grounding the enable pin disconnects the backplane side from the card side, disables the rise-time accelerators, drives ready low, disables the bus precharge circuitry, and puts the part in a low current state. when the pin voltage is driven all the way to v cc , the part waits for data transactions on both the backplane and card sides to be complete before reconnecting the two sides. resistor pull-up value selection the system pull-up resistors must be strong enough to provide a positive slew rate of 1.25 v/ m s on the sda and scl pins, in order to activate the boost pull-up currents during rising edges. choose maximum resistor value using the formula:
where r is the pull-up resistor value in w , v cc(min) is the minimum v cc voltage in volts and c is the equivalent bus capacitance in picofarads (pf). in addition, regardless of the bus capacitance, always choose r 16 k w for v cc = 5.5 v maximum, r 24 k w for v cc = 3.6 v maximum. the start-up circuitry requires logic high voltages on sdaout and sclout to connect the backplane to the card, and these pull-up values are needed to overcome the precharge voltage. see the curves in figures 7 and 8 for guidance in resistor pull-up selection. 30 20 15 21 5 0 0 100 200 300 400 c bus (pf) r pullup (k w ) 25 recommended pull-up r max = 24 k w rise-time > 300 ns sw02115 figure 7. bus requirements for 3.3 v systems 20 15 21 5 0 0 100 200 300 400 c bus (pf) r pullup (k w ) recommended pull-up r max = 16 k w rise-time > 300 ns sw02116 figure 8. bus requirements for 5 v systems minimum sda and scl capacitance requirements the device connection circuitry requires a minimum capacitance loading on the sda and scl pins in order to function properly. the value of this capacitance is a function of v cc and the bus pull-up resistance. estimate the bus capacitance on both the backplane and the card data and clock buses, and refer to figures 7 and 8 to choose appropriate pull-up resistor values. note from the figures that 5 v systems should have at least 47 pf capacitance on their buses and 3.3 v systems should have at least 22 pf capacitance for proper operation. although the device has been designed to be marginally stable with smaller capacitance loads, for applications with less capacitance, provisions need to be made to add a capacitor to ground to ensure these minimum capacitance conditions if oscillations are noticed during initial signal integrity verification.
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 8 hot swapping and capacitance buffering application figures 9 through 11 illustrate the usage of the pca9510 and pca9511 in applications that take advantage of both its hot swapping and capacitance buffering features. in all of these applications, note that if the i/o cards were plugged directly into the backplane, all of the backplane and card capacitances would add directly together, making rise- and fall-time requirements difficult to meet. placing a bus buffer on the edge of each card, however, isolates the card capacitance from the backplane. for a given i/o card, the pca9510 and pca9511 drive the capacitance of everything on the card and the backplane must drive only the capacitance of the bus buffer, which is less than 10 pf, the connector, trace, and all additional cards on the backplane. see application note an10160, hot swap bus buffer for more information on applications and technical assistance. c1 0.01 m f r4 10 k w r5 10 k w power supply hot swap i/o peripheral card 1 r6 10 k w enable v cc sdain sclin sdaout sclout ready gnd card1_sda card1_scl r1 10 k w r2 10 k w v cc sda scl bd_sel backplane backplane connector c3 0.01 m f r8 10 k w r9 10 k w power supply hot swap i/o peripheral card 2 r10 10 k w enable v cc sdain sclin sdaout sclout gnd card2_sda card2_scl c5 0.01 m f r12 10 k w r13 10 k w power supply hot swap i/o peripheral card n r14 10 k w enable v cc sdain sclin sdaout sclout gnd cardn_sda cardn_scl sw02126 r11 10 k w r7 10 k w r3 10 k w ready ready staggered connector staggered connector staggered connector note: the pca9510 and pca9511 can be used in any combination depending on the number of rise time accelerators that are needed by t he system. normally only one pca9511 would be required per bus. figure 9. hot swapping multiple i/o cards into a backplane using the pca9510 and pca9511 in a compactpci, vme, and advancedtca system
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 9 c1 0.01 m f r4 10 k w r5 10 k w i/o peripheral card 1 r6 10 k w enable v cc sdain sclin sdaout sclout acc gnd card_sda card_scl r1 10 k w r2 10 k w v cc sda scl backplane backplane connector c2 0.01 m f c3 0.01 m f r8 10 k w r9 10 k w i/o peripheral card 2 r10 10 k w enable v cc sdain sclin sdaout sclout acc gnd card2_sda card2_scl c4 0.01 m f sw02121 staggered connector staggered connector figure 10. hot swapping multiple i/o cards into a backplane using the pca9510 and pca9511 in a pci system r3 1 k w r2 1 k w c2 0.01 m f r5 10 k w enable v cc sdaout sdain ready sclout sclin gnd r4 10 k w r1 10 k w scl sda v cc scl2 sda2 r drop v cc_low sw02123 figure 11. system with disparate v cc voltages
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 10 absolute maximum ratings limiting values in accordance with the absolute maximum system (iec 134). voltages with respect to pin gnd. limits symbol parameter min. max. unit v cc supply voltage range v cc 0.5 +7 v v n sdain, sclin, sdaout, sclout, ready, enable 0.5 +7 v i i maximum current for inputs 20 ma i io maximum current for i/o pins 50 ma t opr operating temperature range 40 +85 c t stg storage temperature range 65 +125 c t sld lead soldering temperature (10 sec max) +300 c t j(max) maximum junction temperature +125 c note: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability.
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 11 electrical characteristics v cc = 2.7 v to 5.5 v; t amb = 40 to +85 c unless otherwise noted. symbol parameter test conditions limits unit symbol parameter test conditions min. typ. max. unit power supply v cc supply voltage note 1. 2.7 e 5.5 v i cc supply current v cc = 5.5 v; v sdain = v sclin = 0 v; note 1. e 2.8 6 ma i cc(sd) supply current in shut-down mode v enable = 0 v, all other pins at v cc or gnd e 200 e m a start-up circuitry v pre precharge voltage sda, scl floating; note 1. 0.8 1.0 1.2 v v en enable threshold voltage e 0.5 x v cc 0.7 x v cc v v dis disable threshold voltage 0.3 x v cc 0.5 x v cc e v i en enable input current enable from 0 v to v cc e 0.1 1 m a t en enable delay or initialization time e 130 e m s t idle bus idle time note 1. 50 120 250 m s t dis disable time, enable to ready e 15 e ns t stop sda in to ready delay after stop note 7 e 1.3 e m s t ready scl out /sda out to ready note 7 e 1.2 e m s i off ready off state leakage current v en = v cc e 0.3 e m a c i enable capacitance v i = v cc or gnd, note 4 e 2 e pf c o ready capacitance v i = v cc or gnd, note 4 e 2 e pf v ol(ready) low-level output voltage on ready pin i pull-up = 3 ma; v en = v cc; note 1. e e 0.4 v rise time accelerators i pullupac transient boosted pull-up current positive transition on sda, scl, v cc = 2.7 v; slew rate = 1.25 v/ m s note 2. 1 2 e ma inputoutput connection v os inputoutput offset voltage 10 k w to v cc on sda, scl; v cc = 3.3 v; note 1; note 3. 0 65 150 mv f scl_sda operating frequency 0 e 400 khz t plh scl to scl and sda to sda 10 k w to v cc , c l = 100 pf each side e 25 e ns t phl scl to scl and sda to sda 10 k w to v cc , c l = 100 pf each side e 380 e ns c in digital input capacitance note 4 e e 10 pf v ol low-level output voltage input = 0 v, sda, scl pins, i sink = 3 ma; v cc = 2.7 v; note 1 0 e 0.4 v i li input leakage current sda, scl pins = v cc = 5.5 v e e 5 m a
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 12 symbol unit limits test conditions parameter symbol unit max. typ. min. test conditions parameter system characteristics f i2c i 2 c operating frequency 0 e 400 khz t buf bus free time between stop and start condition note 4 1.3 e e m s t hd,sta hold time after (repeated) start condition note 4 0.6 e e m s t su,sta repeated start condition setup time note 4 0.6 e e m s t su,sto stop condition setup time note 4 0.6 e e m s t hd,dat data hold time note 4 300 e e ns t su,dat data setup time note 4 100 e e ns t low clock low period note 4 1.3 e e m s t high clock high period note 4 0.6 e e m s t t clock, data fall time notes 4 and 5 20 +0.1 x c b e 300 ns t r clock, data rise time notes 4 and 5 20 +0.1 x c b e 300 ns notes: 1. this specification applies over the full operating temperature range. 2. i pullupac varies with temperature and v cc voltage, as shown in the typical performance characteristics section. 3. the connection circuitry always regulates its output to a higher voltage than its input. the magnitude of this offset voltage as a function of the pull-up resistor and v cc voltage is shown in the typical performance characteristics section. 4. guaranteed by design, not production tested. 5. c b = total capacitance of one bus line in pf. 6. sda_in/scl_in = 0.1 v, sda_out/scl_out through resistor to v cc . 7. delays that can occur after enable and/or idle times have passed.
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 13 typical performance characteristics sw02152 temperature ( c) 40 +25 +85 2.5 2.3 2.1 1.9 1.7 i cc (ma) 2.4 2.2 2.0 1.8 v cc = 5.5 v v cc = 2.7 v v cc = 3.3 v figure 12. i cc versus temperature. sw01049 temperature ( c) 40 +25 +85 12 8 4 0 i pullupac (ma) 10 6 2 v cc = 5 v v cc = 2.7 v v cc = 3.0 v figure 13. i pullupac versus temperature. sw02153 temperature ( c) 40 +25 +85 450 425 325 t phl (ns) 400 375 350 v cc = 5.5 v v cc = 2.7 v v cc = 3.3 v c in = c out = 100 pf r pullupin = r pullupout = 10 k w figure 14. inputoutput t phl versus temperature. sw02154 r pullup ( w ) 10,000 20,000 30,000 100 80 60 40 90 70 50 0 40,000 v cc = 3.3 v or 5.5 v v out v in (mv) figure 15. connection circuitry v out v in .
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 14 t idle t dis t en sdax/sclx enable ready sw02155 figure 16. timing for t enable , t idle , and t disable t stop t en sclin sclout sdaout enable ready sw02156 sdain figure 17. t stop that can occur after t enalbe
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 15 t ready t en t idle enable ready sw02157 sclin/sdain sclout/sdaout figure 18. t ready delay that can occur after t enalbe and t idle pulse generator v i v o c l= 100 pf v cc definitions r l = load resistor. c l = load capacitance includes jig and probe capacitance r t = termination resistance should be equal to the output impedance z o of the pulse generators. v cc r t d.u.t. r l = 10 k w sw02345 figure 19. test circuitry for switching times
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 16 so8: plastic small outline package; 8 leads; body width 3.9 mm sot96-1
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 17 tssop8: plastic thin shrink small outline package; 8 leads; body width 3 mm sot505-1
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 18 revision history rev date description _2 20041005 product data sheet (9397 750 13998). supersedes data of 2003 dec 18 (9397 750 12561). modifications: ? adescriptiono section on page 2: add fourth paragraph. ? afeatureso section on page 2, last bullet: add a(msop8)o ? add section amaximum number of devices in serieso on page 6. ? section aminimum sda and scl capacitance requirementso on page 7 rewritten ? delete (old) figure 10 arepeater/bus extender application using the pca9510 and pca9511o ? `absolute maximum ratings' table on page 10: add parameters i i and i io . ? electrical characteristics, subsection asystem characteristicso on page 12: change unit for t hd;dat and t su;dat from m s to ns. ? figure 19 modified. _1 20031218 product data (9397 750 12561). ecn 853-2442 01-a14987 dated 15 december 2003.
philips semiconductors product data sheet pca9510; pca9511 hot swappable i 2 c and smbus bus buffer 2004 oct 05 19 purchase of philips i 2 c components conveys a license under the philips' i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011. definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2004 all rights reserved. printed in u.s.a. date of release: 10-04 document number: 9397 750 13998 philips semiconductors data sheet status [1] objective data preliminary data product data product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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